1. Field of the Invention
The present invention relates to a layout designing method for designing a layout of a logic circuit such as a Large-Scale Integrated (LSI) circuit and a Printed Wiring Board (PWB) or a layout of logical connection in such a logic circuit, and in particular, to a crosstalk error control apparatus, a crosstalk error control method, and a crosstalk error control program to suppress a crosstalk error.
2. Description of the Prior Art
When a wiring pitch is large in the designing of a layout of a logic circuit in an LSI circuit or a PWB or a layout of logical connection of such a logic circuit, it is not required to pay attention to influence of crosstalk due to adjacent wiring lines.
However, since the wiring patterns of the LSI circuit and the PWB become finer, the wiring pitch is decreased. Hence the influence of the crosstalk cannot be neglected. Therefore, in the layout designing of logical circuits in the LSI circuit and the PWB as well as the logical connection in such logical circuits, the influence of the crosstalk must be considered. The crosstalk error has been suppressed as below.
For example, according to a first crosstalk error suppress control scheme, when allocation of a wiring pattern is finished, a crosstalk analysis is carried out based on a result of the wiring pattern allocation. The analysis includes, for example, calculation of a quantity of crosstalk between adjacent wiring lines. On the basis of a result of the crosstalk analysis, a net in which a crosstalk error occurs and a wiring pattern of a net having led to occurrence of the crosstalk are corrected to thereby suppress an event of the crosstalk.
According to a second crosstalk error suppress control scheme, in the designing of a wiring pattern, a line length is controlled for a wiring path or route of each net. That is, the length of parallel linear parts of the wiring path is bounded to thereby suppress crosstalk errors.
For example, Japanese Patent Application Laid-open No. 2002-259480 describes a crosstalk avoiding method. The method aims to avoid a crosstalk taking place at simultaneous transition of signals between adjacent inter-cell wiring lines to verify timing of a semiconductor integrated circuit including a plurality of nets in which a driver cell and a driven cell are connected by an inter-cell wiring line to each other. The method includes an extraction step to receive as inputs thereto a net list containing information regarding the nets, timing information including rising and falling information of output signals from each of the driver cells, and reference value information including a driving performance ratio reference value of the driver cell between nets whose wiring lines are adjacent to each other. In the extraction step, according to the timing information, candidate networks for victims (networks in which a crosstalk occurs or in which a crosstalk has occurred) and aggressors (networks causing a crosstalk) are extracted from the net list. The method further includes a calculation step to calculate an output signal waveform from each driver cell of the victims and the aggressors and a determination step of calculating, according to the output signal waveforms, a driving performance ratio between both driver cells, comparing the ratio with the reference value, and determining as a result whether or not the driving performance ratio must be corrected. The method also includes a correction step of determining, if the determination step has asserted that the ratio must be corrected, the driving performance of each of the driver cells of the victims and the aggressors so that the ratio matches with the reference value. As a result, even when an optimal solution cannot be obtained only by changing the driving performance of the driver cells of the victims, optimal driving performance is automatically set to reduce the delay variation due to the crosstalk.
Japanese Patent Application Laid-Open No. 5-342305 describes a crosstalk verification apparatus to automatically verify presence or absence of places where crosstalk likely occurs. The apparatus includes a first allocating or assigning unit to allocate layout pattern data indicating a verification layout pattern to be verified, a second allocating unit to allocate a design rule regarding the verification layout pattern, and a first storage means to store a first criterion for transistor's size that possibly exerts influence of crosstalk and a second criterion regarding transistor's size that is likely affected by crosstalk. The apparatus further includes a first extraction unit connected to the first and second allocating units and the first storage means to process the layout pattern data by referring to the design rule and the first and second criteria. From the transistors of the verification layout pattern, the first extraction module obtains transistors satisfying the first criterion and those satisfying the second criterion. For the selected transistors, the module extracts data of output wiring patterns from the layout pattern data. The apparatus also includes a second storage means to store a third criterion for magnitude of crosstalk noise, a second extraction unit connected to the first extraction unit and the second storage means, and a display connected to the second extraction unit to visually present error positions. The second extraction module calculates according the data of the output wiring pattern, inter-wiring capacity in an overlapped/parallel section between output wiring of each transistor satisfying the first criterion and output wiring of each transistor satisfying the second criterion to obtain, according to the capacity, magnitude of crosstalk noise taking place at each of the rising and the falling of an output signal from the transistor satisfying the second criterion. If the magnitude exceeds the third criterion, the second extraction unit extracts the overlapped/parallel section as an error position.
Japanese Patent Application Laid-Open No. 7-154231 describes a semiconductor integrated circuit including an output circuit in which an internal logic is inserted between a power supply terminal and a ground terminal, and a p-channel MOS transistor and an n-channel MOS transistor are connected in parallel with the internal logic. The output port of the internal logic is connected to gate electrodes of the p-channel and n-channel MOS transistors. The p-channel MOS transistor includes a power supply line connected to a plurality of voltage-drop diodes in a forward direction and in series to lower a high-level output voltage from a Complementary Metal Oxide Semiconductor (CMOS) IC to thereby suppress occurrence of emission noise and crosstalk noise.
However, according to the first crosstalk error suppression control, the crosstalk error cannot be sufficiently removed or suppressed only through the wiring correction in some cases, depending on the density of the wiring of the net in which a crosstalk error has occurred or a net adjacent to the error occuring net. When the wiring is changed to a considerable extent, there exists a fear that the change influences crosstalk noise and path delay in other wiring lines. It is required in such a case to again carry out the wiring correction depending on cases.
For the second crosstalk error suppression control which the gives the condition that any two linear sections of the wiring path do not run parallel beyond a certain length, it is not possible to fully remove or suppress the crosstalk error depending on the wiring density. There also likely exists a case in which the wiring arrangement includes unnecessary bending sections and detours, which thereby deteriorate the wiring layout.
In Japanese Patent Application Laid-open No. 2002-259480, by correcting the driving performance of each driver cell of a victim (a net in which a crosstalk has occurred) and an aggressor (a net having caused the crosstalk), the waveform variation of the output signal waveform on the victim side is reduced to thereby avoid a timing error due to the delay variation caused by the crosstalk. However, consideration has not been given to control of the signal level of the aggressor.
The gist of the technique of Japanese Patent Application Laid-Open No. 5-342305 resides in the automatic verification of presence or absence of places where crosstalk likely occurs, and hence attention has not been given to the suppression of the crosstalk error.
According to Japanese Patent Application Laid-Open No. 7-154231, the CMOS IC of which the output voltage is less than the power supply voltage suppresses the crosstalk noise. However, like Japanese Patent Application Laid-open Nos. 2002-259480 and 5-342305, consideration has not been given to the suppression of the crosstalk error.